PIC18F14K50-I/SS【PDF 49/285 页】IC PIC MCU FLASH 8KX16 20-SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3876

45页 46页 47页 48页 [49页]50页 51页 52页 53页

PIC18F/LF1XK50

DS41350E-page 142

Preliminary

2010 Microchip Technology Inc.

15.2.2

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

Master mode (SCK is the clock output)

Slave mode (SCK is the clock input)

Clock Polarity (Idle state of SCK)

Data Input Sample Phase (middle or end of data

output time)

Clock Edge (output data on rising/falling edge of

SCK)

Clock Rate (Master mode only)

Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

SSPSTAT register, and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored and the write collision detect bit WCOL

of the SSPCON1 register, will be set. User software

must clear the WCOL bit to allow the following write(s)

to the SSPBUF register to complete successfully.

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF of the SSPSTAT register, indicates

when SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. If the interrupt method is not going to

be used, then software polling can be done to ensure

that a write collision does not occur. Example 15-1

shows the loading of the SSPBUF (SSPSR) for data

transmission.

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP STATUS register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 15-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP

BTFSS

SSPSTAT, BF

;Has data been received (transmit complete)?

BRA

LOOP

;No

MOVF

SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF

RXDATA

;Save in user RAM, if data is meaningful

MOVF

TXDATA, W

;W reg = contents of TXDATA

MOVWF

SSPBUF

;New data to xmit

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式